The fabrication of integrated circuits devices is well known. They are manufactured by fabricating a plurality of active devices, such as field effect transistors (FET) with sources, drains and gates, and passive devices on and in a semiconductor wafer substrate, such as silicon. The transistors, which also can be bipolar with emitters, collectors and bases, and the passive devices are connected by a conductive material, such as metal in the form of conductive patterns. Metal, such as aluminum or copper, is used for the first and higher conductive layers or what is called BEOL (Back End of the Line). Doped polysilicon is normally used at the gate of the FET.
When electrical current flows through the metal conductive patterns or interconnections, electromigration or current limiting mechanisms due to heat may occur. These mechanisms grow increasingly severe as the cross-section of the conductive pattern is decreased along with an increase in the current. The result can be failure of one or more integrated circuits. Electromigration is due to metal atoms being pushed by the electron flow comprising the current, in proportion to the current density, and may cause a disconnection of the interconnection or an “open”. For a given current being carried by an interconnection, current density becomes larger, and thus electromigration more severe, as the cross-section of the interconnect becomes smaller with technology scaling. Electromigration is becoming an increasing problem in the BEOL of largely scaled integrated circuit chips with transistors such as FETs, such as CMOS devices, and bipolars devices. In multi-finger applications in which the layout of the devices is such that the metalization is in parallel stripes or fingers, these fingers carry significant current densities and current limiting mechanisms including electromigration are a major concern. Such devices include: power amplifiers, RF switches, I/O drivers, small analog devices operating near peak ft, devices with moderate current densities but operating at high ambient temperature (above 80° C.) or chips that develop a large amount of heat during operation, and any device with long fingers or conductive stripes corresponding to the width of, for example, a channel in a FET.
FIG. 1 shows a graph plotting exponentially the reduction of the wire cross-section with each improved technology generation in which minimum feature size is decreased. The lower plot is for (M1) (first level metal) and the higher plot is for (M2) (second level metal). As shown by the graph, the reduction of the cross-section of the wire is substantial from technology 5 to technology 10. In turn, the current capability of the wire is substantially lowered with the scaling in technology. However, current does not scale in step with the scaling in technology in the above list of applications. For example, a wireless power amplifier (PA) requiring 100 mW of output power for a particular application will be required to achieve this power regardless of the technology. When a constant power is required, the required current actually increases with downward device scaling and improvements in technology because the supply voltage (V supply) is scaled down. FIG. 2 shows this trend of DC power being routed though a minimum width wire with downward device scaling and improvement in technology. (At Technology 7 and beyond, the effect of switching the interconnect metal from aluminum to the more electromigration-resistant metal copper is shown in both FIGS. 1 and 2.) Accordingly, device scaling and technology improvements are amplifying the problem of current limiting mechanisms including electromigration for multi-finger application that carry significant current densities. This device scaling causes an increase in length of the parallel metallization stripes or fingers and a corresponding increase in current density at the end of the fingers.
Table I below is a comparison of different prior art layouts using a common technology, herein Technology 9, and without changing the gate pitch. The (M2), (M3) and (M4) in Table I are identifying the levels of metal from the wafer. The second level metal is (M2) whereas (M3) is the third level metal, and (M4) is the fourth level metal.
TABLE IMAX UNITMETALFINGERIMPROVEMENTLAYOUTLEVELSWIDTH (μm)OVER PCELLRF PCell*20.761.00RF PCell, Wide Metals21.331.75Strap** M2 with M331.401.84Strap M2 with M3,32.523.32wide metalsStrap M2 with M3 and41.682.21M4Strap M2 with M3 and43.364.42M4, wide metalsHalf-Plane*** PCell20.881.16Half-Plane PCell,21.932.54wide metals*PCell is a reference layout for a high-frequency CMOS FET.**Strapping is wiring the same current path using two or more consecutive levels of metal tied together by vias in order to increase the total cross section and carry more current.***Half-Plane is a layout where both the source and drain are each wired to a separate plane of M2 that spans the device over half the M1 finger width.
The above Table I illustrates that, by strapping (M2) with (M3) and (M4), 3.36 um is the widest metal dimension achievable. Compared to the standard RF PCell at 0.76 um metal width and the improvement base of 1.00, this strapped prior art approach has an improvement of a factor of 4.42 over the standard PCell and was the best of all of the prior art approaches.
To operate safely with minimal current limiting mechanisms such as electromigration, a dimension limit is put on the conductive stripe or finger width, which is the wire used to connect the drain and source of a FET or to connect to the collector and emitter of a bipolar transistor. By using a larger gate pitch and wider metal lines, current densities are reduced. However, the disadvantage of this approach is that the metal width that is required can be very significant. For example, a gate finger width of 10 μm would require a (M2) (the second level of metal) width of about 5.8 μm, which requires an intolerable gate pitch to accommodate. Another approach is to strap higher levels of metal over the (M2) finger or stripe. However, the problem with this approach is that parasitic capacitance between adjacent fingers will be increased while the current capability only can be increased slightly. Also, using more metal levels may not be available or feasible in the layout. Another approach is a half-plane, which has no electromigration problems on (M2), but does on the half of the M1 that is not covered by (M2) and therefore still suffers a limit on the maximum width of (M1). Thus, the electromigration safety of the half-plane layout is limited.
Therefore, the layout approach needed in solving current limiting mechanisms including electromigration must 1) permit very long device fingers, 2) be electromigration safe for any number of levels of metals and for all available types of metals, and 3) must not increase gate pitch.